1. Field of the Invention
The present invention relates to a circuit arrangement comprising a matrix-shaped memory arrangement for variably adjustable delay of digital signals, particularly for digital signal processing and communications technology.
2. Description of the Prior Art
Defined delays of digital data streams can be effected as is frequently required in the field of digital signal processing and the field of communications technology by delay apparatus. Defined delays are employed, for example, for the compensation of transit times. Given a constant number of design delay clocks, an arrangement comprising a shift register is generally available as a delay device. When, however, the delay is to be variably adjustable, then certain problems occur given the use of shift registers.
It is also known to delay data streams in defined fashion by way of an arrangement composed of standard circuits and memory modules. In such an arrangement, the component parts of the data stream are deposited with a freely-adjustable memory. This memory is driven by a decoder which is, in turn, driven by one (or more) counters. The duration of the delay is thereby established by the spacing of the counter reset pulses. Since the memory cells of such freely-adjustable memories can only be respectively written or read per clock, the necessity arises of either operating the memories at twice the clock rate or of switching back and forth between two memory units in a multiplex mode. The first solution of this problem has the disadvantage that the maximum data clock frequency can be only half as high as the maximum memory cycle frequency. The solution of the latter problem requires involved logic circuits for address control and a necessary reordering of the data. For an integratable realization of such a circuit arrangement, disadvantages also arise because of the high space requirement of the necessary multiplexers and because of the required, extensive wiring.
German patent application No. P 35 06 603.2, corresponding to the above-referenced U.S. Ser. No. 828,512, discloses a circuit arrangement comprising a matrix-shaped memory for variably adjustable delay of digital signals. This known circuit arrangement comprising a matrix-shaped memory for variably adjustable delay of digital signals essentially contains known three-transistor cells with overlapping write/read cycles as storage elements and comprises a row selector which is clock controlled by an input data clock, continuously steppable and resettable at any time. The row selector comprises two respective signal outputs per selection stage which are offset in phase relative to one another, these respectively selecting a write word line or a read word line. The row selector of this known circuit arrangement is reset with a reset signal preferably derived from the input data clock. The chronological spacing between reset pulses is selected such that it is equal to the required delay time which is to be established between an undelayed data output and the first of m delay data outputs.